VLSI devices normally include several busses for transporting data or address information from point to point in the circuit. These busses often include 16 or 32 lines, which have a rather high capacitance of 5-10 picofarads (pf). To move data from a sender circuit to a receiver circuit, the busses are first precharged by a clock to a high precharge voltage level VPC (such as 3-5 volts) during a first clock phase C1, as shown in FIG. 1. During a second clock period C2, the sender circuit is evaluated by the sending function, and each bus line is either left at the precharged voltage level (FIG. 1b) or is discharged to VSS (FIG. 1a), depending upon whether a "1" or "0" is being transmitted. During a third clock period C3, the user inputs the level on the bus line in the receiver circuit.
The precharge of the bus lines often occurs during a very short (50-100 nsec) interval, which requires large NFETs that never quite reach their final potential of three volts. If, however, PFETs are used by themselves, the PFETs precharge the bus all the way to a full five volts, which is a higher potential than the receiver circuits require, resulting in a waste of power. Such waste occurs because the precharge power is proportional to C.sub.BUS VPC.sup.2 f, in which C.sub.BUS represents the capacitance of the bus line, VPC is the precharge voltage, and f represents the clock frequency. Thus, a five volt precharge dissipates 5.sup.2 /3.sup.2 =25/9 as much power as a three volt precharge.
Thus, the objective of the present invention is to create a voltage-regulated P-channel circuit that precharges the bus line to a predetermined voltage level.